oct 28
Discuss caches and memory hierarchy.
Note that Tuesday's assignment now has some exercises from chapter 6.
6.6, pg 583 : SSD lifetime , various assumptions
6.8, pg 590 : right varies fastest
6.9
L1 cache
L2 cache
SSD solid state disk
HD (spinning) hard disk
SRAM static : fast switch over , multiple transistors, cache "door slam"
DRAM dynamic : generic tiny capacitors ; need to be refreshed (!)
pg 613 : intel core i7 cache system
L1 4 cycles
L2 11
L3 ~35 cycles
details of how caches work :
cache "hit"
cache "miss"
cache line : one chunk of data (fetch more than requested)
cache set : (possibly) several places in cache were a given line might be
called "associativity" ;
E = assoc = 1 => only one place in cache for given line
which increases chance of "thrashing";
if ask for 0,8,0,8 and all map to same cache spot,
miss every time
